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Last updated February 1, 2026
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Vertical dmos gate architecture: BYDRecent Research Landscape

Switching losses and thermal instability in power electronics increase energy waste and risk device failure. These innovations engineer the physical semiconductor cell structure to optimize reverse conduction and current density.

What technical problems is BYD addressing in Vertical dmos gate architecture?

High specific on resistance

(48)evidences

The focus on terminal structures and VDMOS gate architecture indicates a need to mitigate peak electric field concentrations at device edges. Preventing premature dielectric or junction failure extends the operating voltage range and reliability of power apparatus.

Excessive conduction power loss

(8)evidences

Standard insulated gate bipolar transistors lack an inherent body diode for reverse current flow. Solving this eliminates the need for external anti-parallel diodes and reduces footprint.