Data movement bottlenecks in traditional von Neumann architectures drive excessive power consumption and latency. This configuration integrates charge-domain processing directly within 3D NOR-type resistive memory structures to eliminate bus-related energy losses.
Conventional voltage-mode or current-mode in-memory computing suffers from high power consumption and signal noise during multiply-accumulate operations. Shifting to the charge domain reduces static power dissipation and improves computational precision in dense crossbar arrays.